Job Description and Requirements

Owns cross team planning, collaboration, and coordination ensuring that geographically distributed teams are well-aligned
Measure project and performance using appropriate systems, tools and techniques
Establish and maintain relationships with cross-functional teams, internal and external customers
Create and maintain comprehensive project documentation

Key Qualifications & Experience

Familiarity with physical design of analog and mixed signal CMOS circuits
Exposure and knowledge of the full design cycle from RTL to GDSII, including chip level
Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers
Solid organizational skills including attention to detail and multi-tasking skills
Autonomous, timely decision maker and able to cope with interrupts
Experience with advanced FinFET nodes, TSMC 16 nanometer and below
Exposure to SERDES design architectures, and layout
Experience with Design tool(s): Custom Compiler, Cadence Virtuoso or equivalent
Verification tools: ICV, Calibre
Experience in working with Jira/Atlassian (or other such) tools
Strong working knowledge of MS Office Suite of applications

Preferred Experience

Typically requires MSEE or BSEE with a minimum of 2 years of related experience
Previous analog layout or ASIC physical design experience
Solid understanding of digital / mixed signal flows and SOC integration challenges

R&D Engineering, Staff Engineer